Manufacturability-aware physical IC design processes, which take into account such factors as yield and reliability, are becoming increasingly important aspects in bridging the gap between what is designed and what is actually produced or fabricated. Traditionally, physical IC design verification has focused primarily on design verification rules-based approaches. For example, design rule checking (DRC) is an area of electronic design automation (EDA) that enables IC designers to determine whether a particular physical layout design satisfies a series of parameters, also referred to as design rules. Design rules are typically provided by IC manufacturers (e.g., foundries) to enable IC designers to verify the “correctness” of their physical layout patterns. In this manner, design rules are often associated with specific manufacturing processes. Thus, a set of design rules may specify certain IC features (e.g., geometric element) and/or connectivity restrictions to ensure sufficient margins are present to account for the variability in one or more manufacturing processes. As such, design rule checking is a major step during physical verification of physical IC layout configurations performed by the IC designers.
As the demand for increased feature densities grows and manufacturing processes evolve, design rule sets are becoming increasingly more complex. Accordingly, one objective of design verification is to achieve a certain level of yield and reliability for a particular physical IC layout pattern. If design rules are violated the design may not be functional. To meet this goal of improving yield and/or reliability, design verification has evolved from simple measurement and Boolean check-based techniques to processes that modify existing features, insert new features, and check entire designs for process limitations. A completed layout consists not only of the geometric representation of the design itself, but also data that provides support for manufacturing the design. While design verification processes do not necessarily ensure a particular physical IC layout pattern will operate correctly, these processes are constructed to at least verify that the physical configuration meets certain processing constraints for given design types and/or manufacturing process technologies. Thus, as physical IC layout patterns become more complex, the execution of design verification techniques is becoming evermore computationally intensive. For instance, some design verification techniques, if executed on a single processing platform, may require several days (if not weeks) to generate results. In competitive environments like the semiconductor industry, however, design cycles need to be as short as possible; lengthy design verification processes only burden such efforts.
The above-described process-driven yield enhancement is performed prior to mask data preparation (MDP), which precludes the possibility of analysis of layout changes on certain design metrics. Thus, potential post-layout enhancements, including changes to the graphic data system (GDS) stream for opportunistic insertion of redundant vertical interconnect accesses (VIAs) and shapes to enhance manufacturability, or shape shifting to improve critical areas (e.g., those susceptible to random defects), are not possible. Further, as technology scales, design analyses must increasingly account for the design performance impact of manufacturing enhancements and the computational scalability of manufacturing enhancement techniques as layout data size quadruples with every technology node.
A need, therefore, exists for methodology enabling the enhancement and/or modification of layout data in the IC design stage with semantics passed from manufacturability analysis/yield enhancement tools at the manufacturer back to the designer. There exists a particular need for methodology enabling the insertion of manufacturability and/or yield-enhancing design constructs during the design stage (e.g., layout synthesis, more specifically, in detail routing) based on analysis from the pre-MDP or IC manufacturability analysis stages. The pre-MDP stage entails detailed analysis of the layout for ensuring its manufacturability in the process, through the use of various design for manufacturability (DFM) tools.